1. Field of the Invention
The present invention relates to a semiconductor process, and more particularly, to a semiconductor process capable of avoiding diode leakage problem.
2. Description of Related Art
With the rapid miniaturization and high level integration of integrated circuits, feature line width, contact area and junction depth are continuously minimized. To effectively improve the working characteristics of devices and reduce the resistance of resistors and the resistor/capacitor signal transmission delay, a silicide layer is often formed at junctions to lower contact resistance.
In the conventional self-aligned silicide process, a nickel silicide (NiSi) layer is normally formed on the surface of the gate and the source/drain of a metal-oxide-semiconductor (MOS) transistor. However, the presence of a nickel silicide layer frequently produces piping problem. In other words, after forming the nickel silicide layer, the nickel silicide may diffuse laterally into the silicon substrate and the channel and lead to current leakage. To resolve the piping problem of the nickel silicide layer, a pre-amorphous implantation (PAI) process is often carried out which implants indium or arsenic atoms into the surface of the silicon substrate before forming the nickel silicide layer so as to prevent any lateral diffusion of the nickel silicide.
FIGS. 1A through 1C are schematic cross-sectional views showing a conventional semiconductor process for preventing the lateral diffusion of nickel silicide. First, as shown in FIG. 1A, a substrate 100 is provided. The substrate 100 has a shallow trench isolation (STI) structure 102 formed therein. Furthermore, the substrate 100 has a metal-oxide-semiconductor transistor 104 formed thereon. The MOS transistor 104 includes a gate 106, a gate dielectric layer 108, spacers 110 and source/drain regions 112. Then, a pre-amorphous implantation 114 is performed on the substrate 100 to form an amorphous silicon layer 116 on the source/drain regions 112 (as shown in FIG. 1B). Next, as shown in FIG. 1C, a self-aligned silicide process (salicide) process is carried out to form a nickel silicide layer 120 on the source/drain regions 112 and the gate 106.
However, in the aforementioned process of forming the amorphous silicon layer 116, the amorphous silicon layer 116 often has a greater thickness toward the corner regions 118 of the shallow trench isolation structure 102. Therefore, the subsequently formed nickel silicide layer 120 will have a greater thickness as the same corner regions 118 so that diode leakage problem may occur.